The present invention relates to a voltage booster circuit; and, in particular, the invention relates to a voltage booster (step-up) circuit which is suitable for boosting a power supply in an integrated semiconductor circuit packaged in an integrated circuit, such as a microprocessor and the like, which requires a voltage having a wide operating range.
Recently, for a microprocessor, a demand for low voltage operation and low power consumption has been increasing in order to meet the demand to mount the microprocessor into a portable machine. Namely, in the case of a microprocessor that is normally comprised of CMOS logic circuits, if a power supply voltage which exceeds a threshold voltage Vth of its MOS transistor is available, the logic operation of each CMOS gate which constitutes its logic circuits is ensured, although the operation speed thereof may drop somewhat. If, however, its power supply voltage drops, for example, from 5 volts to below 2 volts, because a voltage across the gate and the source of the MOS transistor approaches the threshold voltage Vth of MOS transistor, the on-resistance of the MOS transistor increases. In particular, in a circuit that uses a transfer gate, in a MOS transistor which constitutes the transfer gate, voltage across the gate and the source may drop below Vth according to the terminal voltage that the transfer gate transfers. In such a case, the on-resistance of its transfer gate becomes extremely great, thereby preventing transfer of a normal voltage level. Further, in a memory module, such as a mask ROM or the like, a drop in the power supply voltage means a drop in a word line drive voltage in a memory mat. Namely, it means that among a plurality of memory MOS transistors constituting the memory mat, for those memory MOS transistors whose gate is connected to the word lines, a voltage across the gate and the source thereof drops to cause a drain current of the memory MOS transistor to attenuate, thereby resulting in an increase in data read time.
Therefore, in order to cope with a case having a specification of a low power supply voltage, for example, below 2 V, a desired operation is ensured even under a low power supply voltage by adoption of a method as described, for example, in JPA Laid-Open No. 8-149801, whereby its low power supply voltage is boosted for driving its transfer gate (MOS side gate) and memory module word lines.
In the related art described above, a technique is adopted wherein, in principle, a stepped-up voltage, corresponding to twice the power supply voltage VCC which is applied to a power supply terminal, is constantly produced in a boost cycle, including a charging period and a charge transfer period; and, wherein, more specifically, a first terminal of a booster capacitance, which is charged to a level of the power supply voltage VCC, is further charged by applying the power supply voltage via a switching circuit in the charging period thereof, and in the charge transfer period after the charging period, the charge having been accumulated in the booster capacitance is transferred to a load via an output terminal. Therefore, if an integrated semiconductor circuit device having a conventional built-in booster circuit is used as a power supply voltage VCC, which has a relatively high voltage region, for example, 4V or more, a resulting step-up voltage produced by the booster circuit may exceed a withstand voltage of the device (MOS transistor), thereby deteriorating reliability of the system and/or causing breakdown of the devices. However, if a clamp circuit (which is comprised of three PMOS transistors connected in series, and a threshold voltage of each PMOS transistor is set at Vthp) is connected in parallel between the first terminal of the booster capacitance and the terminal of the power supply, namely in parallel with the switching circuit, the booster circuit can be clamped at a voltage of power supply voltage VCC plus 3 times |Vthp|.
Nowadays, however, withstand voltages of the devices are on the decrease along with the trend for devices having finer patterns, and, therefore, an upper limit in the range of power supply voltage VCC and an allowable application voltage (or withstand voltage of the device) are coming into close proximity. Therefore, in the aforementioned voltage clamping method, on the side of the upper limit in the range of power supply voltage VCC, there is a concern that the clamp voltage may exceed its allowable application voltage.
On the other hand, in order to lower the clamp voltage, a voltage drop in the voltage clamp circuit may be minimized, for example, by reducing the number of series connections of PMOS transistors that constitute the voltage clamp circuit. However, this method, if applied to a case having a specification of the power supply voltage VCC in a low voltage range, in contrast to the above, the boost efficiency thereof drops, so that the clamp voltage cannot be reduced simply. Further, as for the clamp voltage, because a fluctuation as great as an integer times the number of connections, i.e., three times in the case of three series connections, results in a condition relative to a fluctuation of a device parameter, i.e., Vthp, of each of the PMOS transistors that constitute its voltage clamp circuit, attainment of compatibility between the low voltage range and the high voltage range for ensuring a high boost efficiency in the low voltage range, while limiting the boost voltage in the high voltage range, is difficult. Still further, because there exists a certain time lag until the voltage clamp is enabled after the voltage clamp circuit is operated, there may arise a peak voltage in excess of its clamp voltage due to that time lag.
Further, as a method for preventing the occurrence of an over-voltage, a depletion type NMOS transistor (hereinafter referred to as a D-MOS) may also be connected between the power supply and the power supply terminal, as disclosed in the aforementioned JPA, so as to clamp the voltage itself to be applied to the power supply terminal. If this method is adopted, in a range of power supply voltage VCC above a threshold voltage |VthD| of the D-MOS, because the voltage of the power supply terminal can be clamped at a level of |VthD|, a boost voltage can certainly be suppressed to approximately twice of |VthD|.
In contrast, however, in a case where the power supply voltage VCC drops below |VthD| a boost voltage twice as great as the power supply voltage VCC is produced. Therefore, if a D-MOS is used, a boost voltage of 2 times |VthD| must exist in a voltage range that has as its low limit voltage a voltage used by a circuit, and as an upper limit voltage, an allowable application voltage. In addition, in consideration of the fluctuation in device parameters as described above, it becomes more difficult to suppress the boost voltage within a predetermined voltage range with a drop in the upper limit of the allowable application voltage. Still further, use of a D-MOS causes increases in the number of mask sheets and processes in the manufacture of semiconductor chips, thereby increasing the cost of manufacture disadvantageously. For example, even when a D-MOS is used in circuits other than the booster circuit mounted on the same chip as their components, unless each D-MOS thereof is operable at the same threshold voltage as the booster circuit device, additional masks and/or additional processes will be required eventually.
An object of the present invention is to provide for a booster circuit apparatus that can regulate a level of voltage boosting according to the magnitude of its power supply voltage.
In order to accomplish the above-mentioned object of the invention, a booster circuit is provided by a method which is comprised of the steps of: applying a power supply voltage to one terminal of a booster capacitance interposed between a power supply terminal and an output terminal in a charging period in a boosting cycle which includes the charging period and a charge transfer period, and applying a reference voltage of a reference potential to the other terminal of said booster capacitance; applying said power supply voltage to the other terminal of said booster capacitance in the charge transfer period thereafter, and transferring charges accumulated in said booster capacitance from said one terminal thereof to said output terminal; and regulating said charging period according to the magnitude of said power supply voltage.
In the construction of the above-mentioned booster circuit, when its power supply voltage is below a predetermined voltage, said charging period is regulated in accordance with a drop of said power supply voltage, and when said power supply voltage is in excess of said predetermined voltage, said charging period is set at zero or regulated to be shortened in accordance with the magnitude of the power supply voltage. Further, instead of regulating the charging period in accordance with the magnitude of the power supply voltage described above, it is possible to regulate the amount of charges to be accumulated in the booster capacitance during the charging period in accordance with the magnitude of the power supply voltage, or to regulate the magnitude of current to be supplied to the booster capacitance during the charging period in accordance with the magnitude of the power supply voltage as well. Still further, it is possible to provide a discharge period prior to the charging period in the boosting cycle, and wherein, during this discharge period, a voltage of the same potential is applied to both the terminals across the boosting capacitance to discharge the charges from the boosting capacitance.
Further, according to another aspect of the invention, a voltage boosting circuit system and a method therefore is provided, in which a power supply voltage is applied to one terminal of a booster capacitance that is interposed between a power supply terminal and an output terminal during a charging period in a boosting cycle which includes the charging period and a charge transfer period, and a voltage of a reference potential is applied to the other terminal of the booster capacitance; application of the power supply voltage to said one terminal of the booster capacitance is stopped for a period of time during the charging period which is determined in accordance with a magnitude of the power supply voltage, and at the same time, a voltage at the reference potential is applied to said one terminal of the booster capacitance so as to discharge the charges in the booster capacitance; and, thereafter, said power supply voltage is applied to the other terminal of said booster capacitance so as to cause the charges accumulated in the booster capacitance to be transferred from said one terminal thereof to said output terminal during the charge transfer period. In construction of this booster circuit of the invention, additional elements may be added which allow for the discharge period during said charging period described above to be adjusted to make the charging period longer if said power supply voltage becomes higher than a pre-set voltage and in accordance with an increase of said power supply voltage, and, on the other hand, if said power supply voltage drops below said preset voltage, allowing for the discharge period during said charging period to be adjusted to become zero.
According to still another aspect of the invention, a booster circuit is provided, which is comprised of a booster capacitance which is interposed between a power supply terminal and an output terminal; a discharge command signal output means for outputting a discharge command signal which specifies said discharge period in the boosting cycle which includes a discharge period, a charging period and a charge transfer period; a charge command signal output means for outputting a charge command signal which specifies said charging period; a control signal output means for outputting a control signal corresponding to a start of said charging period, then, after elapse of a period of time which is determined by a magnitude of the power supply voltage, for stopping outputting said control signal; a first switching means for applying the power supply voltage to one terminal of said booster capacitance in response to a discharge command signal corresponding to a start of said discharge period; a bias switch means for applying the power supply voltage to the other terminal of the booster capacitance until said charge command signal is input, and applying a voltage of a reference potential to the other terminal of the booster capacitance in response to an input of a charge command signal corresponding to a start of said charging period; a second switching means for applying the power supply voltage to said one terminal of the booster capacitance in response to the charge command signal corresponding to the start of the charging period; and a charge transfer means which interrupts its charge transfer path connecting said one terminal of the booster capacitance and said output terminal during a period of time while the control signal from said control signal output means is being output, and establishes said charge transfer path while the output of said control signal from said control signal output means is stopped, and wherein said charge command signal output means adjusts the period of time for generation of said charge command signal in accordance with the magnitude of said power supply voltage. In construction of this booster circuit according to the invention, additional or alternative elements as follows may be added.
(1) In place of the second switching means, a bias means may be provided for applying a bias voltage to the one terminal of the booster capacitance in accordance with the power supply voltage.
(2) Omitting the discharge command signal output means, and in place of the first and the second switching means, another switching means may be provided for applying the power supply voltage to the one terminal of the booster capacitance in response to a control signal.
(3) In place of the second switching means, a bias means may be provided for supplying a bias current corresponding to the power supply voltage to the one terminal of the booster capacitance in response to the control signal.
(4) Said charge command signal output means is comprised so as to allow the period of time for generation of said charge command signal to be adjusted to become longer if the power supply voltage falls below a preset voltage in accordance with a drop of said power supply voltage, and to be adjusted to zero if said power supply voltage exceeds said preset voltage.
According to a still further aspect of the invention, a booster circuit is provided, which is comprised of a booster capacitance which is interposed between a power supply terminal and an output terminal; a charge command output means for outputting a charge command signal which specifies the charging period in a boosting cycle which includes a charging period and a charge transfer period; a control signal output means for outputting a control signal corresponding to a start of said charging period, and thereafter, stopping the outputting of said control signal after elapse of a period of time which is determined by a magnitude of the power supply voltage; a discharge command signal output means for outputting a discharge command signal only for a period of time to be determined by a magnitude of the power supply voltage when said outputting of said control signal is stopped and during said charging period; a first switching means for applying a voltage of a reference potential to one terminal of the booster capacitance in response to said discharge command signal; a second switching means for applying the power supply voltage to the one terminal of the booster capacitance in response to said control signal; a bias switch means for applying the power supply voltage to the other terminal of the booster capacitance before said charge command signal is input, and applying a voltage of a reference potential to the other terminal of the booster capacitance in response to an input of the charge command signal corresponding to a start of said charging period; and a charge transfer means for interrupting a charge transfer path connecting the one terminal of the booster capacitance and said output terminal while the charge command signal from said charge command signal output means is being output, and establishing said charge transfer path therebetween while said outputting of said charge command signal from said charge command signal output means is stopped. In the construction of this booster circuit according to the invention, the following elements may be added thereto.
The discharge command signal output means operates to allow a period of time for generation of said discharge command signal to be adjusted to become longer, if the power supply voltage becomes higher than a preset voltage, in accordance with an increase in said power supply voltage, and to become zero, if the power supply voltage becomes smaller than said preset voltage.
According to the above-mentioned features of the invention, because one terminal of the booster capacitance is supplied with the power supply voltage, while the other terminal thereof is supplied with the voltage of the reference potential, and the charging period is adjusted in accordance with the magnitude of the power supply voltage, it becomes possible to regulate the level of a step-up voltage in accordance with the magnitude of the power supply voltage. In particular, when the power supply voltage is below the preset voltage, the charging period is adjusted to become longer corresponding to a drop in the power supply voltage. When the power supply voltage exceeds the preset voltage, the charging period is adjusted to become zero or shortened corresponding to an increase in the power supply voltage, thereby making it possible to generate a step-up voltage at a level corresponding to a prescribed power supply voltage when the power supply voltage drops below the preset voltage, and to adjust the level of a step-up voltage to zero when the power supply voltage exceeds the preset voltage, or suppress the same in accordance with an increase in the power supply voltage. Therefore, a preferred boosting efficiency can be attained without the boosting level exceeding the allowable voltage.
More particularly, in the case when the charging period is adjusted in accordance with the magnitude of the power supply voltage, a step-up voltage HVs which appears at the one terminal of the booster capacitance, assuming under no load condition or a saturated condition for the step-up voltage saturated by indefinite cycles of boosting, is expressed by the following equation (1),
HVs=VCC+VC1xe2x80x83xe2x80x83(1),
where VCC is a power supply voltage, and VC1 is a potential difference immediately prior to the boosting operation between both the terminals across the boosting capacitance. Assuming that an accumulated charge in booster capacitance C1 is Q1, and the coefficient of capacitance is C1, the potential difference VC1 between both the terminals thereof is expressed by equation (2)
VC1=Q1/C1xe2x80x83xe2x80x83(2).
In the above equation (2), by increasing or decreasing Q1 in accordance with a magnitude of power supply voltage VCC, the level of step-up voltage HVs can be controlled appropriately. Namely, for example, in a higher voltage region where the power supply voltage VCC exceeds the preset voltage level, if VC1 is reduced by decreasing Q1, the level of step-up voltage HVs can be suppressed to a smaller value. Further, in a lower voltage region where the power supply voltage VCC is below the preset voltage level, if VC1 is increased by increasing Q1 in contrast to the above, an appropriate level of step-up voltage HVs can certainly be maintained. Further, the charge Q1 of booster capacitance C1 which can be specified by charge current IC and its conduction period, namely, by charging period tw, is expressed by the following equation (3)
Q1=ICxc3x97twxe2x80x83xe2x80x83(3).
In the above equation (3), by specifying the charging period tw belonging to the boosting cycle, such as to reduce tw in the higher voltage region where the power supply voltage VCC exceeds the preset voltage, and to increase tw in the lower voltage region, where power supply voltage VCC is below the preset voltage level, the charge Q1 can be adjusted to decrease or increase, thereby allowing for the level of step-up voltage HVs to be regulated by the charging period.